1. Field of the Invention
The present invention concerns determining an expected amount of clock signal jitter on a clock distribution network, and may include selecting particular combinations of characteristics for circuitry of a device such that jitter is reduced
2. Related Art
FIG. 1A illustrates a power supply 101 connected to integrated circuitry device 100 having a clock 144 and clock distribution network 142, according to the prior art. Coordinated timing of the operation of circuitry 145 throughout device 100 depends on clock signals distributed to circuitry 145 by network 142. Jitter introduces uncertainty in the timing of those clock signals. If jitter is too large or circuitry 145 is not adequately tolerant of the jitter, circuitry 145 throughout device 100 will not operate in proper coordination, thus resulting in malfunctions, which may include erroneous calculations, deadlock, or the like.